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S75WS-P based MCP/POP Products
1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash (NOR Interface) S30MS-P (NAND Interface) ORNANDTM Flash pSRAM Type 2
Data Sheet (Advance Information)
S75WS-P based MCP/POP Products Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S75WS-P_00
Revision 02
Issue Date September 6, 2006
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S75WS-P based MCP/POP Products
September 6, 2006 S75WS-P_00-02
S75WS-P based MCP/POP Products
1.8 Volt-only x16 Simultaneous Read/Write, Burst Mode Flash (NOR Interface) S30MS-P (NAND Interface) ORNANDTM Flash pSRAM Type 2
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 to 1.95V Flash access time: 80 ns (NOR), 25 ns (ORNAND) Flash burst frequencies: 66 MHz, 80 MHz, 108 MHz pSRAM Access time: 70 ns, 20 ns (Page) pSRAM burst frequency: 66 MHz, 80 MHz, 104 MHz Package:
- 12 x 12 mm PoP - 9 x 12 mm, 115-ball MCP
Operating Temperature
- -25C to +85C (wireless)
The S75WS series is a product line of MCPs or POPs, and consists of: One S29WS-P NOR flash memory die One or more S30MS-P NAND interface ORNAND flash memory die pSRAM Type 2 For detailed specifications, please refer to the individual data sheets
.
Document S29WS-P 256Mb pSRAM Type 2 S30MS-P
Publication Identification Number (PID) S29WS-P_00 psram_24 S30MS-P_00
Publication Number S75WS-P_00
Revision 02
Issue Date September 6, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advance
Information)
1.
Product Selector Guide
Device Model Number LW 256 256 512 80 VS Flash Density (Mb) pSRAM Density (Mb) ORNAND Density (Mb) Flash Speed (MHz) 66 104 Type 2 FMC115: MCP 12 x 9 mm pSRAM Speed (MHz) pSRAM Supplier Package AMB128: POP 12 x12 x 1.15 mm
S75WS256PEFKFF S75WS256PEFJF5
2. MCP Block Diagram
A0-A23 A0-A23
RDY
RDY
DQ0-DQ15
DQ0-DQ15
CLK AVD# F-CE# OE# F-RST# F-ACC F1-WP# WE#
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256P Flash Memory
VSS
VSS
VCC VCCQ
F-VCC
A0-A23
WAIT#
DQ0-DQ15
R1-CE#
CLK AVD# CE# OE# LB# UB# WE# CRE
R-LB# R-UB# R-CRE
256 Mb UtRAM Memory
VSS VCC VCCQ
R-VCC
I/O0-I/O15
I/O0-I/O15
N-RY/BY#
RB#
N-CLE N-CE# N-ALE N-RE# N-WP# N-WE#
CLE CE# ALE RE# WP# WE#
MS512P x16 ORNAND Memory
VSS PRE
N-VSS N-PRE
VCC
N-VCC
2
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Data
Sheet
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Information)
3. POP Block Diagram
A0-A23 A0-A23
F-RDY/R-WAIT
RDY
DQ0-DQ15
DQ0-DQ15
CLK AVD# F-CE# OE# F-RST# F-ACC F1-WP# WE#
CLK AVD# CE# OE# RESET# ACC WP# WE#
WS256P Flash Memory
VSS VSSQ
VSS VSSQ
VCC VCCQ
F-VCC VCCQ
A0-A23
WAIT#
DQ0-DQ15
R-CLK R-CE#
CLK AVD# CE# OE# LB# UB# WE# MRS
R-LB# R-UB# R-MRS
256Mb UtRAM Memory
VSSQ VSS VCC VCCQ
R-VSS R-VCC
I/O0-I/O15
I/O0-I/O15
N-RY/BY#
RB# ACC
N-CLE N-CE# N-ALE N-RE# N-WP# N-WE#
CLE CE# ALE RE# WP# WE#
MS512P x16 ORNAND Memory
VSS PRE N-PRE
VCC
N-VCC
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Data
Sheet
(Advance
Information)
4. Connection Diagrams
4.1 12 x 12 mm PoP
1 A NC B NC C RFU D RFU E R-MRS F RFU G RFU H R-CE# J RFU K N-ALE L N-RY/BY# N-RE# M F-RDY/ R-VSS R-WAIT N N-VCC R-VCC P DQ14 R VCCQ T RFU U NC V NC NC RFU DQ12 DQ10 VCCQ DQ8 R-UB# F-ACC F-RST# R-LB# DQ6 VCCQ DQ4 DQ2 RFU NC NC NC RFU DQ13 DQ11 VSSQ DQ9 RFU N-WP# F-WP# RFU DQ7 VSSQ DQ5 DQ3 RFU NC NC RFU N-PRE RFU VSSQ VSSQ VCCQ DQ15 DQ1 DQ0 R-VCC F-VCC VSS RFU RFU F-CE# N-CLE R-CLK F-CLK N-CE# RFU RFU NOR/pSRAM Shared Only RFU WE# OE# VSS R-VCC AVD# RFU N-WE# RFU Flash Shared Only RFU RFU RFU pSRAM Only A1 A23 RFU Reserved for Future Use R-VSS R-VSS RFU NOR Flash Only NC RFU A3 A5 A7 VSS A9 A11 A13 A15 VSS A17 A19 A21 RFU NC NC No Connect NC A0 A2 A4 A6 N-VCC A8 A10 A12 A14 F-VCC A-16 A18 A20 A22 NC NC All Shared 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Legend
ORNAND Flash Only
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Data
Sheet
(Advance
Information)
4.2
9 x 12 mm, 115-ball MCP
1 A NC B NC C AVD# D
N-RY/ BY#
2
3
4
5
6
7
8
9
10
NC
NC
NC Legend
NC
NC
NC
VSS
CLK
RFU
IO15
IO14
IO13
IO12
NC
Reserved for Future Use
F-WP#
A7
R-LB#
F-ACC
WE#
A8
A11
IO11
IO10
No Connect
E N-RE# F N-CE# G N-VCC H N-VSS J N-CLE# F1-CE# K N-ALE# R-CE# L N-WE# N-WP# M NC N NC P NC NC NC NC NC NC NC RFU RFU VSS F-VCC IO0 IO1 IO2 IO3 PRE DQ8 DQ2 DQ11 RFU DQ5 DQ14 IO4 IO5 DQ0 DQ10 F-VCC R-VCC DQ12 DQ7 VSS IO6 OE# DQ9 DQ3 DQ4 DQ13 DQ15 R-MRS IO7 NOR Flash/ pSRAM Shared Only A0 VSS DQ1 RFU RFU DQ6 RFU A16 N-VSS A1 A4 A17 RFU A23 A10 A14 A22 N-VCC A2 A5 A18 RDY A20 A9 A13 A21 IO8 NAND Flash Only A3 A6 R-UB# F-RST# RFU A19 A12 A15 IO9 NOR Flash Only
pSRAM Only
4.3
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150xC for prolonged periods of time.
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Data
Sheet
(Advance
Information)
4.4
Look-ahead Ballout for Future Designs
1 A NC B NC C RFU R-VSS/ NC D RFU E D-BA0/ P1-CRE F D-RAS#/ D-CAS#/ F-RAS# F-CAS# G D-WE# F-VSS H D1-CS#/ D2-CS#/ P1-CE# P2-CE# J
F3-CE#/ F4-CE#/ D-BA1/ P2-CRE/S1-CS2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Legend
NC
A0
A2
A4
A6
F-VCC2
A8
A10
A12
A14
F-VCC1
A-16
A18
A20
A22
NC
NC
Address
NC
RFU
A3
A5
A7
F-VSS
A9
A11
A13
A15
F-VSS
A17
A19
A21
RFU
NC
NC
No Connect (corner balls)
R-VSS/ NC
RFU Data
A1
A23
A24 Reserved for Future Use
A25
A26 Ground
N-WE#
A27 Power
R-VCC F-ADV#/ P-ADV# Control F-WE#/ F-OE#/ P-WE#/S-WE# P-OE#/S-OE# D-CLK# F-CLK#
N2CE#/P1-CE2 N1CE#/P2-CS2
K N-ALE L N-RDY/ N-RE# BSY# M
F-WAIT/ P-WAIT/P-RDY
N-CLE
D-CLK/ F-CLK P-CLK
F2-CE#/ F1-CE# N3CE# F-VSS F-DPD
R-VSS
N F-VCC2 R-VCC P DQ14 R VCCQ T D-CKE N-RES#/ NC U NC V NC NC RFU DQ12 DQ10 VCCQ DQ8
D-DM1/ P-UB#/ S-UB#
R-VCC F-VCC1
DQ15
DQ1
DQ0
VSSQ
VSSQ
VCCQ
N-PRE
F-CKE
NC
N-MRES# DQ13
DQ11
VSSQ
DQ9
D-DQS1 N-WP2#/ F-WP# D-DQS0 F-WP2#
DQ7
VSSQ
DQ5
DQ3
RFU
NC
NC
F-VPP/ F-RST# D-DM0/ DQ6 N-ACC P-LB#/S-LB#
VCCQ
DQ4
DQ2
RFU
NC
NC
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S75WS-P based MCP/POP Products
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Data
Sheet
(Advance
Information)
5.
Input/Output Descriptions
Table 5.1 identifies the input and output package connections provided on the device. Table 5.1 Input/Output Descriptions (Sheet 1 of 2)
Symbol Amax-A0 DQ15-DQ0 F-CE# OE# WE# F-VCC F-VCCQ VSS RFU RDY Signal Type Input I/O Input Output Input Power Power Ground -- Output Description NOR Flash Address inputs Flash Data input/output, shared between NOR and ORNAND Flash; shared with IO15-IO0 for ORNAND NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode. Output Enable input. Asynchronous relative to CLK for Burst mode. Write Enable input. NOR Flash device power supply (1.7 V - 1.95V). Input/Output Buffer power supply. Ground Reserved for Future Use Flash ready output. Indicates the status of the Burst read. VOL = data valid. The Flash RDY pin is shared with the WAIT pin of the pSRAM. NOR Flash Clock, shared with CLK of burst-mode pSRAM. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. NOR Flash Address Valid input. Shared with AVD# of burst-mode pSRAM. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs NOR Flash hardware reset input. VIL= device resets and returns to reading array data NOR Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors. NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. Chip-enable input for pSRAM Mode Select Register (pSRAM). For Type 2 only. pSRAM Power Supply Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Do Not Use Command Latch Enable: The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE# signal while CE# is low and CLE is High. Address Latch Enable: The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE# if CE# is low and ALE is High. Input data is latched if CE# is low and ALE is Low. X X WS (NOR) X X X X X X X X X X X X pSRAM X X X MS (ORNAND)
CLK
Input
X
X
AVD#
Input
X
X
F-RST# F-WP# F-ACC
Input Input Input
X X
X
R-CE# R-MRS R-VCC R-UB# R-LB# DNU N-CLE
Input Input Power Input Input -- Input
X X X X X
X
N-ALE
Input
X
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Data
Sheet
(Advance
Information)
Table 5.1 Input/Output Descriptions (Sheet 2 of 2)
Symbol N-CE# Signal Type Input Description Chip Enable: The device enters a low-power Standby mode when the device is in Ready mode. The CE# signal is ignored when the device is in a Busy state (RY/BY# = L), such as during a Page Buffer Load or Erase operation, and will not enter Standby mode even if the CE# input goes high. The CE# signal may be inactive during the Page Buffer write and Page Buffer load of the array data. Write Enable: The WE# signal is used to control the acquisition of data from the I/O port. Read Enable: The RE# signal controls serial data output. Data is available tREA after the falling edge of RE#. The internal column address counter is also incremented (Address = Address + 1) on this falling edge. Write Protect: The WP# signal is used to protect the device from accidental programming or erasing. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. WS (NOR) pSRAM MS (ORNAND)
X
N-WE# N-RE#
Input Output
X
X
N-WP#
Input
X
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S75WS-P based MCP/POP Products
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Data
Sheet
(Advance
Information)
6.
Ordering Information
The order number is formed by a valid combinations of the following:
S75WS
256
P
EF
KF
F
LW
0 PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER Refer to the Valid Combinations Table PACKAGE DESCRIPTOR Depends on Character 12. For a more detailed description see Table 6.1. PACKAGE TYPE & MATERIAL SET HF = 1.2mm MCP FBGA, Pb-free KF = 1.2mm POP FBGA, Pb-free JF = 1.4mm MCP FBGA, Pb-free CellularRAM DENSITY D0 = 128 Mb PROCESS TECHNOLOGY P = 90 nm, MirrorBitTM Technology CODE FLASH DENSITY 256 = 256Mb 512 = 512Mb PRODUCT FAMILY S71WS Stacked Products (MCP/PoP) 1.8 V NOR Flash with pSRAM
Table 6.1 Character Position Descriptions
Character 14 Description Character 12 Character 14 0 1 2 3 4 H, J, or G 5 6 7 8 9 A B D F G K H J K L M 14x14 mm 15x15 mm 15x15 mm 17x17 mm 17x17 mm 152 160 160 192 192 0.50 mm 0.45 mm 0.50 mm 0.45 mm 0.50 mm 9x12 mm 9x12 mm 11x13 mm 11x13 mm 11x13 mm 11x11 mm 11x11 mm 12x12 mm 12x12 mm 14x14 mm 115 137 84 115 137 112 112 128 128 152 0.45 mm 0.50 mm 0.45 mm 0.50 mm 0.45 mm Package Area 7x9 mm 7x9 mm 8x11.6 mm 8x11.6 mm 9x12 mm Package Ball Count 56 80 64 84 84 0.35 mm Raw Ball Size
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Data
Sheet
(Advance
Information)
6.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
S75WS-P Valid Combinations Device Package & Material Set KF Package Descriptor F 5 Model Number LW 0, 2, 3 (Note 1)s JF VS 80 104 Type 2 9 x 12 mm Packing Type NOR Flash Speed (MHz) 66 pSRAM Speed (MHz) 104 pSRAM Supplier Type 2 Package Type 12 x 12 mm (Note 2) Package Markings
S75WS256PEF Notes: 1. Packing Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S and packing type designator from ordering part number.
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S75WS-P based MCP/POP Products
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Data
Sheet
(Advance
Information)
7.
7.1
Physical Dimensions
AMB128-- 128-ball 12 x 12 mm Package-on-Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD SD
7
A B C D E F G
PIN A1 CORNER
SE
7
E eE
0.15 C (2X)
18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 2 1
H J K L M N P R T U V
E1
B
BOTTOM VIEW
TOP VIEW A A2 A1
6
0.15 C (2X) 0.20 C
C
0.10 C
SIDE VIEW b
M M C AB C
128X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD SE 0.45 AMB 128 N/A 12.00 mm x 12.00 mm PACKAGE MIN --0.39 0.55 NOM ------12.00 BSC 12.00 BSC 11.05 BSC 11.05 BSC 18 18 128 128 2 0.50 0.65 BSC 0.65 BSC 0.325 BSC 0.55 MAX 1.15 --0.70 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PERIMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 6 7 NOTE 4. 5. 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3559 \ 16-038.56 \ 4.28.6
C3~C16, D3~D16, E3~E16, F3~F16 DEPOPULATED SOLDER BALLS G3~G16, H3~H16, J3~J16, K3~K16 L3~L16, M3~M16, N3~N16, P3~P16 R3~R16, T3~T16
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Data
Sheet
(Advance
Information)
7.2
FMC115 -- 115-ball 12 x 9 mm MCP
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD SE 0.35 FMC 115 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.17 0.96 NOM ------12.00 BSC. 9.00 BSC. 10.4 BSC. 7.20 BSC. 14 10 115 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A3,A4,A5,A6,A7,A8 B3,B4,B5,B6,B7,B8,C1 N3,N4,N5,N6,N7,N8 P3,P4,P5,P6,P7,P8 0.45 MAX 1.40 --1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 6 7 NOTE 4. 5. 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3603 \ 16-038.19 \ 9.6.6
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Data
Sheet
(Advance
Information)
8.
8.1
Revision History
Revision 01 (May 5, 2006)
Initial release.
8.2
Revision 02 (September 6, 2006)
Added the MCP S75WS256PEF
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
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